1. Field of the Invention
This invention relates to integrated circuit manufacturing, and more particularly, to a method for cleaning particles from a semiconductor topography that has been polished using a fixed-abrasive polishing process, wherein the particles are provided to the topography from an abrasive polishing surface. The particles are removed from the semiconductor topography by applying a cleaning solution to the topography using either (a) an acid and a peroxide or (b) an acid oxidant.
2. Description of the Relevant Art
Fabrication of an integrated circuit involves numerous processing steps. After implant regions (e.g., source/drain regions) have been placed within a semiconductor substrate and gate areas defined upon the substrate, an interlevel dielectric is formed across the topography to isolate the gate areas and the implant regions from overlying conducting regions. Interconnect routing is then placed over the interlevel dielectric and connected to the implant regions and/or the gate areas by ohmic contacts formed through the interlevel dielectric. Alternating levels of interlevel dielectric and interconnect may be placed across the semiconductor topography to form a multi-level integrated circuit.
As successive layers are deposited across previously patterned layers of an integrated circuit, elevational disparities develop across the surface of each layer. If left unattended, the elevational disparities in each level of an integrated circuit can lead to various problems. For example, when a dielectric, conductive, or semiconductive material is deposited over a topological surface having elevationally raised and recessed regions, step coverage problems may arise. Step coverage is defined as a measure of how well a film conforms over an underlying step and is expressed by the ratio of the minimum thickness of a film as it crosses a step to the nominal thickness of the film over horizontal regions. Also, stringers may arise from incomplete etching over severe steps. Furthermore, correctly patterning layers upon a topological surface containing fluctuations in elevation may be difficult using optical lithography. The depth-of-focus of the lithography alignment system may vary depending upon whether the resist resides in an elevational "hill" or "valley" area The presence of such elevational disparities therefore makes it difficult to print high resolution features.
Chemical-mechanical polishing ("CMP") is a technique commonly employed to planarize or remove the elevational fluctuations in the surface of a semiconductor topography. A conventional CMP process involves placing a semiconductor wafer face-down on a polishing pad which lies on or is attached to a rotatable table or platen. A popular polishing pad medium comprises polyurethane or polyurethane-impregnated polyester felts. During the CMP process, the polishing pad and the semiconductor wafer are rotated relative to each other as the wafer is forced against the pad. An abrasive, fluid-based chemical suspension, often referred to as a "slurry", is deposited onto the surface of the polishing pad. The slurry fills the space between the polishing pad and the wafer surface such that a chemical in the slurry may react with the surface material being polished. The rotational movement of the polishing pad relative to the wafer causes abrasive particles entrained within the slurry to physically strip the reacted surface material from the wafer. The pad itself may also physically remove some material from the surface of the semiconductor topography.
In order to achieve planarization of the semiconductor topography, elevationally raised regions must be removed at a substantially faster rate than elevationally recessed regions. Unfortunately, the difference in polish rate that can be achieved between the high elevation regions and the low elevation regions is somewhat limited by the use of a slurry in the conventional CMP process. In particular, the slury, being a relatively viscous fluid, flows to the elevationally recessed regions of the topography where it can react with the surface material, releasing it from bondage with the bulk of the material. Because of the toxic nature of some of its effluent components, the slurry waste must be disposed of and subjected to waste treatment after planarization is complete. The disposal and waste treatment of the slurry effluent significantly increases the cost of manufacturing an integrated circuit.
To avoid the problems associated with the conventional CMP process, a more recently developed polishing process known as the "fixed-abrasive" polishing process may be employed to planarize a semiconductor topography. The fixed-abrasive process involves placing a liquid which is substantially free of particulate matter between the surface of the topography and an abrasive polishing surface of a rotating polishing pad. Since no slurry is required, the time consuming and costly disposal of such a slurry may be avoided.
The liquid applied to the polishing surface in a fixed abrasive process may comprise deionized water or an acid diluted with water, depending upon the features of the topography being polished. The polishing surface comprises a polymer-based matrix entrained with particles selected from the group consisting of cerium oxide, cerium dioxide, aluminum oxide, silicon dioxide, titanium oxide, chromium oxide, and zirconium oxide. The abrasive polishing surface belongs to a polishing pad that is substantially resistant to deformation even when placed across an elevationally recessed region of relatively large lateral dimension (e.g., over 200 microns lateral dimension). Therefore, the pad is non-conformal to the underlying surface and thus does not come in contact with elevationally recessed regions of the surface. It is believed that the particles dispersed throughout the abrasive polishing surface in combination with the polishing liquid interact chemically and physically with the elevated regions of the topography to remove those regions. However, the liquid alone is believed to be incapable of removing the topography in elevationally recessed regions. Therefore, preferential removal of high elevation regions relative to low elevation regions is possible using the fixed-abrasive polishing process.
Some of the particles in the abrasive polishing surface of the polishing pad may be dislodged from the surface during polishing. The particles may thus accumulate upon the surface of the semiconductor topography being polished. Adhesion forces between dielectric surfaces (e.g., silicon dioxide) and the particles (e.g., CeO.sub.2) are quite strong, such that the particles particularly adsorb on dielectric surfaces. It is believed that a high zeta potential, i.e., electric static or charge difference, exists between the particles and the dielectric, causing the particles to "stick" to the dielectric. The presence of such particles on the semiconductor topography may scratch the surface of the topography and contaminate the ensuing integrated circuit. Considering the minute dimensions of integrated circuit features, even the tiniest defect in the semiconductor topography can render the ensuing integrated circuit inoperable.
A post-planarization cleaning process is therefore commonly employed to eliminate the abrasive particles from the semiconductor topography. The cleaning process typically involves three main steps. First, the polished surface of the semiconductor topography is buffed at a relatively low pressure for approximately 15 to 30 seconds using the polishing pad. Second, deionized water is directed to another pad softer than the polishing pad (e.g., a Politex Pad commercially available from Rodel Products Corp.) as the topography is buffed by the pad at a relatively low pressure for approximately 30 to 45 seconds. Unlike the polishing pad, this pad does not have particles fixed in the pad. Third, polyvinylalcohol ("PVA") brushes apply a solution comprising ammonium hydroxide and deionized water to the surface of the topography while concurrently mechanically scrubbing that surface for approximately 60 to 90 seconds. A special machine (e.g., the SYNERGY Integra.TM. commercially available from OnTrak Systems Inc.) is needed to perform the PVA brush scrub step.
The post-planarization cleaning process has several drawbacks, for example, some particles nonetheless remain on the surface of the polished semiconductor topography once the cleaning process is completed. The presence of such particles may be detrimental to the operation of the ensuing integrated circuit. Furthermore, the combined costs of the machine, the PVA brushes, and the extra pad required for the post-planarization cleaning procedure are relatively high. Also, the number of wafers that may be cleaned at the same time is somewhat limited by the number of tools having the pads and brushes required for the cleaning. Further, the number of wafers that may be buffed on a single pad is generally 5 or less. The considerable amount of time required to clean all of the wafers being processed might be better spent fabricating subsequent layers of those wafers. It would therefore be desirable to develop a more effective, cheaper, and faster post-planarization cleaning process.